ELASTIX LOW POWER DESIGN SOLUTIONS

Designing for low power is a key requirement for the majority of chip designs. Most existing solutions attack the power problem by optimizing the logic design to use lower power elements or structures or to break the design into different domains based on performance/power requirements. However, these techniques do not address a fundamental cause of excess power consumption – the inherent variability present in chip designs.

Elastix has developed patent-pending technologies that leverage variability to dramatically lower both worst-case power and average power for a given chip design.

Additional information about the Elastix technology can be found in:

• Whitepaper
• Frequently Asked Questions

The Challenge of Low Power Design

The conventional chip design process focuses effort on mitigating the effects of variability by designing for the worst-case corner conditions. On the surface this makes sense as maximizing yield for a given design is an economic must. However, optimizing the design for the worst-case performance corner guarantees that the majority of yielding chips are consuming more power than is necessary or desirable.  In fact, there can be as much as a 3x difference in power consumption between yielding chips that are near the slow corner versus chips that operate near the fast corner.  In other words, the operating conditions (clock rate and supply voltage) imposed by designing for a minority of chips operating at the slow corner causes the majority of chips to consume excess power.

Elastix Technology

Elastix’ patent-pending technology measures the effects of variability in each individual chip and allows the chip to dynamically adjust its operating conditions to lower power consumption. In order to achieve this, Elastix utilizes its patent-pending technologies for elastic clocks and elastic voltage scaling. These two technologies work together to minimize power consumption while maintaining the required operating performance of the chip.

Elastic clocks track variability, and clock the circuitry to run close to the actual speed of the logic. When the logic runs slow (because the corner of the die or the die is slow, the voltage is low, the temperature is high, or the logic values are such), the clock runs slow, and vice-versa.

Elastic voltage scaling recognizes that the supply voltage can also be scaled to meet performance needs while minimizing power consumption.  By constantly measuring the operating performance of the chip (in concert with elastic clocks), the supply voltage can be dynamically tuned to eliminate wasted power while still allowing each chip to meet its performance targets.

Elastic clocks and elastic voltage scaling are both realized by inserting a small amount of specialized circuitry into the chip design. Elastix software tools implement the elements for elastic clocks and voltage scaling in the standard ASIC design flow with minimal impact to the usage of existing tools, such as logic synthesis, placement, routing, timing analysis, formal verification, and test.

Chip designs that incorporate elastic clocking and voltage scaling can achieve lower maximum power consumption and lower average power consumption without compromising design performance.