Elastix offers innovative, patent-pending solutions that dramatically lower on-chip power consumption.

Low power is a key metric for almost all chip designs. While there are techniques and architectures that can help design for reduced power, they do not address the fundamental issue of wasted power caused by variability.

Variability in sub-90nm processes causes most chips to consume more power than is either necessary or desirable. The distribution of power consumption on a chip-by-chip basis due to variability can be very wide – often as much as 3x from lowest power to highest power.  The traditional “design for the worst case” approach actually exacerbates the problem. By designing for the worst case corner, the majority of chips end up being less energy efficient than necessary to achieve the desired performance target.

Elastix’ unique solution leverages variability to deliver two key benefits:

• Reduction of worst-case power consumption
• Lowers average power consumption across all yielding chips

The Elastix solution relies on the synergy between two key patent-pending technologies: elastic clocks and dynamic scaling of elastic voltages. It is fully compatible with and leverages existing chip design flows and tools. Read more about our unique solutions here.

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